One of the most basic demands in the art of semiconductor memory devices is to realize memory devices which feature high speed performance and low production cost per bit. Incessant research and development efforts have therefore been made to increase the cell densities of semiconductor memory devices to meet such a demand.
One important approach to implementation of a high-density semiconductor memory device is apparently to use shrunk design rules in fabricating the device because such shrunk design rules result n significant reduction in the area which each of the memory cells of the memory cell array occupies on a single semiconductor substrate. From another point of view, however, the use of shrunk design rules in fabricating a semiconductor memory device gives rise to an increase in the current density of the various on-chip control circuits of the memory device. Unless substantial reduction is achieved in the voltage to be distributed to such control circuits of the memory device, there would be caused generation of heat from the conductors included in the circuits and disconnection or breaks of the conductors due to electromigration.
A high-density semiconductor memory device thus uses an on-chip voltage stepdown circuit to reduce the reference voltage supplied from an off-chip source, as well known in the art. Such a voltage stepdown circuit is typically composed of a combination of two metal-oxide-semiconductor field-effect transistors connected between the reference voltage source and each of the control circuits provided in the memory device. Each of these field-effect transistors is fabricated to have a certain threshold voltage through appropriate selection of, principally, the thickness of gate oxide layer of the transistor. Furthermore, each of the transistors forming the voltage stepdown circuit has its channel region dimensioned to provide a width-to-length ratio which is large enough to supply a sufficient current to the individual control circuits of the memory device. The voltage stepdown circuit composed of the field-effect transistors thus designed occupies a disproportionally large area of the semiconductor substrate, with a consequent penalty of reducing the proportion of the substrate area available for the memory cell array. This is objectionable for the purpose of increasing the integration density of the memory cells which can be fabricated on the single substrate.